Field programmable gate arrays (FPGAs) are the defining element of today's high density digital circuits. Presco has been using the Xilinx Logic Cell Arrays since their inception in the mid-1980s, becoming one of the earliest factory supported FPGA design centers in the nation. Since that time, FPGA cost per gate has approximated the Moore's Law curve for computers and memories, yielding a 2:1 improvement in cost every two years. Corresponding improvements in density and speed have propelled FPGAs to the forefront of modern design practice, featuring sub-nanosecond gate delays and multi-million gate capacities.

Not Just A Box of Gates

Many of today's circuit designs feature only two substantial component types: memory chips and FPGAs. Consider the features of a Xilinx Virtex chip, the XC2V1000-FG256:
This is a one million gate device in a 17 mm square package. Compared to yesterday's PALs and medium scale logic, the XC2V1000 amounts to a 5000 chip circuit housed in 0.5 square inches of board space. The image just below is a floor plan for a much smaller XCV100 device which has been configured for a video processing algorithm. At only one tenth the size of the XC2V1000, it's still a great deal of circuitry.

Here are some features of the XC2V1000 field programmable gate array:

• The XC2V1000 has 40 internal BlockRAM memories of 18 Kbits. Used as a PCI bus burst buffer, a BlockRAM provides a depth of 512 words - far beyond the size of any standard PCI controller. Used as a line buffer, a full 2K x 8 line of video can be stored.
  
  
• The Virtex Digital Clock Manager (DCM) provides an on-board PLL to match internal and external clocks to within 150 psec. The DCM can multiply, divide, or phase shift an input frequency to generate additional on-chip or off-chip clocks, each of which can remain locked to the input crystal. These clocks can operate in spread spectrum mode to reduce radiated emissions for FCC compliance.
  
  
• Virtex2 supports multiple input/output standards, including high speed interfaces such as LVDS and differential PECL. A special double data rate (DDR) feature inside each IOB permits operation at speeds of up to 840 MHz.
  
  
• At these high interface speeds, terminated transmission lines are the rule for good signal integrity. The Virtex2 IOB features a built-in, adjustable termination resistor which eliminates the need for most on-card termination networks. This removes hundreds of components from the PC card (along with their attendant problems concerning placement, soldering and reliability).

The image below is from an FPGA die editor, showing the details inside one of the logic blocks. In the earliest days of FPGA technology, entire designs were accomplished directly in the editor, but this quickly became impractical as die size increased. Later designs were implemented using schematics or other picture-based tools.

Today, Presco's FPGA development methodology is based on a hardware descriptor language (VHDL or Verilog) using the latest third party software to insure good die utilization and excellent simulation support. We have an impressive store of intellectual property that can be used to shorten your design cycle: check out our innovative FIFO design for a concept that is far superior to others in the industry. Test bench generation for large FPGAs can consume as much time as the chip design itself, and this often becomes the limiting factor in completing a design. Our proprietary compiled VHDL Test Bench capability produces a 10X improvement in test bench development time.