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| Take
the High Risk Out of High Speed |
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At
Presco, the term "high speed" refers to digital and
analog circuits that typically operate at frequencies below
1 GHz. For the most part, these circuits rely on conventional
PC board materials and components. We have all witnessed "high
speed" digital circuits which fail to work properly because
of problems with power supplies, bypassing, or signal integrity.
Here are a few things that we do at Presco to produce reliable
high speed circuit cards:
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It all
starts with power and ground: you need to deliver these "signals"
to your circuit devices at extremely low impedances. Presco's
designs use thin core circuit card sections (two foils separated
by a very thin dielectric layer) to deliver power and ground
to the integrated circuits. This lowers the power plane impedance
10X, reducing ground bounce that would otherwise degrade circuit
performance. The cost of thin core construction is minimal
compared to the alternative outcomes.
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Everyone
recognizes the need for bypassing power supplies, but few
do it properly. Simply placing a capacitor near each power
pin won't do the job because the capacitor itself has significant
series inductance, and its connections to ground and power
(through circuit card vias) add further inductance. Our solution
is to position a thin core pair of foils just below the ICs
to minimize the series inductance of the power supply vias.
Note the hierarchy of capacitors shown at left next to an
FPGA. A 33 uF tantalum capacitor provides low speed response,
augmented at mid-frequencies by an SMT603 monolithic ceramic
capacitor (at center).
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The two unusual caps at top and bottom are 8 leg ultra-low
inductance devices, also shown in the close-up to the below-right.
These capacitors reduce parasitic inductance by 6:1 as compared
to a more conventional component, greatly extending the
useful frequency range of the assembly.
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Essentially
all signal traces must be treated as impedance controlled transmission
lines. Designers tend to forget that it is NOT the clock frequency
that matters, but the edge rate of the transitions. Even a 10
MHz circuit needs controlled impedance traces if the edges are
crisp. Xilinx FPGAs permit edge rates to be softened for non-critical
signals and they even offer adjustable internal termination
resistors, so not every signal line requires a visible termination
component.
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Here are some words you probably hear every day: "synchronous
design using worst case timing analysis". The secret is
to actually do synchronous design and to perform the
worst case timing analysis for every signal. It's easy
to do using the modern synthesis and simulation tools, and it
greatly improves reliability. |
Move
Slow to Get High Throughput
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lot of "high speed" designs are actually high throughput
problems like those encountered in video displays, image processing,
DSP, and pattern recognition. For most of these situations,
high throughput can be obtained without resorting to high clock
rates. See the Neural
Net Engine for an example
of doing billions of computations per second using a small circuit
operating at only 40 MHz. This was accomplished by revamping
the underlying neural net algorithm to work more efficiently
in a parallel hardware architecture - an example of what we
call "architectural speed". |
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Clock
Distribution Matters!
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As
circuit speeds continue to increase, there is no way to avoid
the need for precise clock distribution. For a video digitizer
working at 108 MHz (SXGA pel rate) the three separate color
channels should be time matched to within 1 nsec to avoid artifacts
in the resulting image. |
It is very difficult to achieve this level of accuracy with
conventional clock distribution trees, even using PLL repeaters
or ECL circuitry. Presco has pioneered a method for achieving
200 psec clock skews throughout a multi-card system, with clock
adjustability of 50 psec. |
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