Low Noise Analog Design
A significant portion of Presco’s work occurs in scientific, industrial and medical instrumentation. Every instrument maker seeks high performance and inevitably this depends on the sensor and its supporting electronics. Proper sensor selection, biasing and power supplies are all critically important. Modern practice is to convert the sensor signal to digital form as soon as possible (see our discussion of A/D conversion) so the demand for low noise analog circuit design has declined, leaving a scant few of us who are skilled in the art.
Presco has more than 30 years experience in the design of instrumentation front end circuitry. During that time we’ve “rescued” a surprising number of instruments that suffered from poor analog circuit design. A memorable instance was a measurement-while-drilling (MWD) system which required detection of faint, low bandwidth acoustic pulses. The manufacturer complained about the performance from their new 16 bit A/D converter. Presco performed a simple shorted inputs test that showed only 8 useful bits at the A/D converter. Everything else was noise! We designed a new front end circuit with quieter power supplies and improved common mode rejection that delivered a 64x improvement in signal quality.
A higher frequency acoustic front end occurred in an ultrasound instrument for inspecting solid fuel rocket motors. The manufacturer had sought design assistance from a nationally prominent consulting firm but the results failed to achieve critical performance goals A particularly difficult specification concerned accurate peak detection for the 10 MHz acoustic probe. Direct digitization would have required a sample frequency above 1 GHz – very expensive at the time. Presco designed an innovative analog peak detector with sub-nanosecond aperture time that solved the problem, acquiring the peak signal and presenting it to an inexpensive low speed A/D converter.
Many of our design cycles involve spectrometers – infrared, visible, reflectance, ATR, mass spec, FITR, atomic absorption. This has given us broad exposure to a number of different detectors which are based on detecting light, ions, vibration and thermal changes. For instance, we developed the electronics for a DTGS (thermal) detector for an FTIR spectrometer and are currently working on a photoconductive MCT (Mercury-cadmium-telluride) detector design.
For another client, we designed the electronics package for a DNA sequencer that uses ion sensitive FETs to measure the time development of hydrogen ions that are shed as bases get integrated into a new DNA strand. To achieve the time resolution and dynamic range for this experiment, our design contains four 250 Msps 16-bit ADCs. A single circuit card contains the low noise front end and digitizers, plus all of the supporting circuitry to process a billion samples per second. The circuitry includes three FPGAs communicating by 3.2 GHz SERDES links, an 800 MHz PowerQUICC processor, DDR memories and Gigabit Ethernet. Despite the heavy concentration of digital circuitry, this circuit card maintains a noise floor of just 20 uV RMS which is very close to the theoretical minimum. An especially challenging feature of this design cycle was the long observation time required for completing the DNA sequence. This brought sub-1 Hz frequencies into play, making 1/f noise a critical performance parameter for the circuitry. These low frequency effects are poorly understood by most design teams.
Another critical, and often overlooked, design aspect in designing low noise front-end electronics is clock jitter. When digitizing a slewing signal, jitter on the sample clock translates into an amplitude error due to positional shift. We pay particular attention to how clocks are generated and distributed to minimize this type of “noise”. In the DNA instrument just cited, we employed a sub-psec jitter crystal clock followed by a frequency synthesizer with just 850 femto-seconds of jitter. At these jitter levels it is imperative that clocks not be generated by the FPGAs in the circuit – their internal ground bounce causes unavoidable clock jitter that is typically 100x too big.