At Presco, the term “high-speed” refers to digital and analog circuits that typically operate at frequencies from tens of MHz up to a few GHz. For the most part, these circuits rely on conventional PC board materials and components. We have all witnessed high-speed digital circuits which fail to work properly because of problems with power supplies, bypassing, or signal integrity. Here are a few things that we do at Presco to produce reliable high-speed circuit cards.

It all starts with power and ground: you need to deliver these “signals” to your circuit devices at extremely low impedances. Presco’s designs use thin core circuit card sections (two foils separated by a very thin dielectric layer) to deliver power and ground to the integrated circuits. This lowers the power plane impedance by as much as 10X, reducing ground bounce that would otherwise degrade circuit performance. The cost of thin core construction is minimal compared to the alternative outcomes. Everyone recognizes the need for bypassing power supplies, but few do it properly. Simply placing a capacitor near each power pin won’t do the job because the capacitor itself has significant series inductance, and its connections to ground and power (through circuit card vias) add further inductance. Our solution is to position a thin core pair of foils just below the ICs to minimize the series inductance of the power supply vias.

Essentially all signal traces in a high-speed digital circuit must be treated as impedance controlled transmission lines. Designers tend to forget that it is NOT the clock frequency that matters, but the edge rate of the transitions. Even a 10 MHz circuit needs controlled impedance traces if the edges are crisp. Some FPGAs and CPLDs permit edge rates to be softened for non-critical signals and they even offer adjustable internal termination resistors, so not every signal line requires a visible termination component. Here are some words you probably hear every day: “synchronous design using worst-case timing analysis”. The secret is to actually do synchronous design and to perform the worst-case timing analysis for every signal. It’s easy to do using the modern synthesis and simulation tools, and it greatly improves reliability.

Move Slow to Get High Throughput

A lot of “high speed” designs are actually high throughput problems like those encountered in video displays, image processing, DSP, and pattern recognition. For most of these situations, high throughput can be obtained without resorting to high clock rates. See the Neural Net Engine for an example of doing several billion computations per second using a small circuit operating at only 40 MHz. This was accomplished by revamping the underlying neural net algorithm to work more efficiently in a parallel hardware architecture – an example of what we call “architectural speed”.

Clock Distribution Matters!

As circuit speeds continue to increase, there is no way to avoid the need for precise clock distribution. For a video digitizer working at just 108 MHz (SXGA pel rate) the three separate color channels should be time matched to within 1 nsec to avoid artifacts in the resulting image. It is very difficult to achieve this level of accuracy in a large system with conventional clock distribution trees, even using PLL repeaters or ECL circuitry. Presco has pioneered a method for achieving 200 psec clock skews throughout a multi-card system, with clock adjustability of 50 psec.

FPGAs: The Cost Effective Solution

Field programmable gate arrays (FPGAs) are the defining element of today’s high-density digital circuits. Presco has been using the Xilinx Logic Cell Arrays since their inception in the mid-1980s, becoming one of the earliest factory-supported FPGA design centers in the nation. Since that time, we’ve developed support for additional FPGA manufacturers including Lattice and Altera. FPGA cost-per-gate has approximated the Moore’s Law curve for computers and memories, yielding a 2:1 improvement in cost every two years. Corresponding improvements in density and speed have propelled FPGAs to the forefront of modern design practice, featuring sub-nanosecond gate delays and multi-million gate capacities.

A Turbocharger for FPGA Development

Presco’s FPGA development methodology is based on a hardware descriptor language (VHDL or Verilog) using the latest third-party software to insure good die utilization and excellent simulation support. We have an impressive store of intellectual property that can be used to shorten your design cycle: check out our innovative FIFO design for a concept that is far superior to others in the industry. Test bench generation for large FPGAs can consume as much time as the chip design itself, and this often becomes the limiting factor in completing a design. Our proprietary compiled VHDL Test Bench software produces a 10X improvement in test bench development time.